Impinj Delivers Reprogrammable Nonvolatile Memory IP Breakthrough – AEON®/MTP World's First 2.5V Floating Gate NVM in TSMC's 65 Nonometer Process
Leading logic nonvolatile memory (NVM) intellectual property (IP) supplier, Impinj, Inc., today announced that the company’s multiple-time programmable AEON®/MTP memory designed with 2.5V floating-gate transistors has been silicon-verified in Taiwan Semiconductor Manufacturing Co.’s (TSMC’s) 65 nm LP process.
Seattle, WA September 26, 2007 - Leading logic nonvolatile memory (NVM) intellectual property (IP) supplier, Impinj, Inc., today announced that the company’s multiple-time programmable AEON®/MTP memory designed with 2.5V floating-gate transistors has been silicon-verified in Taiwan Semiconductor Manufacturing Co.’s (TSMC’s) 65 nm LP process. A semiconductor technology breakthrough that leverages Impinj’s extensive semiconductor design expertise and TSMC’s advanced manufacturing capability, AEON/MTP is the first available NVM IP based on floating gate technology with 2.5V transistors. Impinj is also developing AEON/MTP NVM cores in TSMC’s 45 nm processes to address escalating demand from leading-edge system-on-chip (SoC) designers for logic NVM in industry-leading process geometries.
Embedded in more than 600 million chips from leading semiconductor companies, AEON/MTP cores allow many more IC designs to leverage the benefits of multiple-time programmable (MTP) NVM in standard logic CMOS processes. Multiple-time programmable NVM provides significant SoC design flexibility and testability advantages over one-time programmable NVM, including security key refresh capability, in-field user data configuration and in-field performance optimization.
The 65 nm AEON/MTP product meets the following performance specifications:
- Availability in 32 bit to 8k bit configurations for maximum design flexibility
- 15k write-cycle endurance for frequent in-field updating or reprogramming
- 10-year data retention for long product life
- -40 to +125°C operating temperature for high demand industrial applications
“The availability of AEON/MTP in 65 nm processes dispels a long-held industry misconception that floating gates manufactured in 2.5V processes do not retain charge,” said Larry Morrell, vice president and general manager of IP Products at Impinj. “AEON/MTP NVM with 2.5V floating gate transistors has been put through rigorous testing and its reliability and performance have been proven.”
Impinj’s AEON/MTP cores in TSMC’s 65 nm process are available in November to qualified customers with broad availability in the first quarter of 2008. Development of AEON/MTP cores in TSMC’s 45 nm process is underway with planned availability in late 2008.
To request datasheets and additional information about Impinj's AEON logic nonvolatile memory, please visit support.impinj.com.
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Wednesday, September 26, 2007
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